Home Publications


"An Object-Oriented Layered Approach to Interfaces for Hardware/Software Codesign of Embedded Systems"
Gardner, W. B., M. Serra
31st Hawaii International Conference on System Sciences (HICSS-31), Jan 1998
[Abstract][Article in Postscript]

"On-line and off-line testing with shared resources: a new BIST approach"
Sun, X. and M. Serra
IEEE Trans. on CAD, accepted August 1997.

"Concurrent Simulation of Heterogeneous Multiprocessor Embedded Systems."
Gardner, W., and M. Serra
Proc. of 7th Int. Symp. on IC Technology, Systems & Application, 1997.
[Article in PDF format]

"Pseudo-Random Pattern Generation and Fault Coverage of Delay Faults with Non Linear Finite State Machines with High Entropy"
Serra, M. and G.L. Chen
Proc. IEEE On-Line Testing Workshop
[Article in PDF format]

"Digital IC Testing: an Introduction"
Serra, M.
The Electrical Engineering Handbook, (R.C. Dorf, Editor), CRC Press, new and revised edition, 1997.

"A new DFT methodology for sequential circuits"
Costi, C., M.Serra, D. Sciuto
Jetta, Vol.7, No.3, 1996.

"Test sequences embedding with cellular automata"
Fummi, F., D. Sciuto, and M. Serra
Proc. IEEE Int. On-Line Testing Workshop

"Sequential logic minimization based on functional testability"
Fummi, F., D. Sciuto, and M. Serra
Proc. EDAC/ETC/EuroAsic, pp. 207-211

"Synthesis for testability of large complexity controllers"
Fummi, F., D. Sciuto, and M. Serra
Proc. IEEE Int. Conf. on Circuits & Devices

"Test pattern embedding in sequential circuits through cellular automata"
Fummi, F., D. Sciuto, and M. Serra
Proc. VLSI

"The concatenation and partitioning of Linear Finite State Machines"
Sun, X., E. Kontopidi, M. Serra and J.C. Muzio
Int. Journal of Electronics, 78, no. 5, pp. 809-839

"A functional approach to delay faults test generation for sequential circuits"
Fummi, F., and M. Serra
Proc. EDAC/ETC/EuroAsic, pp. 51-57

"Design and implementation of a merged on-line/off-line self-testable architecture"
Sun, X., and M. Serra
IEEE Symposium on Defect and Fault Tolerance, pp. 247-254

"Merging concurrent checking and off-line BIST"
Sun, X., and M. Serra
Proc. of IEEE International Test Conference, pp. 958-967.

"State Assignment and Testability of PLA-based Finite State Machines"
Buonanno, G., and M. Serra
Microprocessing and Microprogramming, Elsevier/North Holland, 35, pp. 391-398

"Tables of linear hybrid 90/150 cellular automata,"
Slater, T. and M. Serra
UVic Computer Science Technical Report DCS-105-IR, 1989.

"The selection of primitive polynomials to reduce aliasing,"
Serra, M. and J.C. Muzio
Pacific Northwest Test Workshop, 1991.

"Cellular automata techniques for compaction based BIST"
Miller, D.M., J.C. Muzio, M. Serra, X. Sun, S. Zhang, and R.D. McLeod
Proc. IEEE Int. Symp. on Circuits & Systems

"The generation of primitive polynomials in GF(9) with independent roots"
Gulliver, T.A., M. Serra and V.K. Bhargava
Int. Journal of Electronics, 71, no. 4, pp. 559-576

"Data compaction for bridging faults"
Muzio, J.C. and M. Serra
Computer Systems, Science and Engineering, 6, pp. 131-142

"Concurrent checking and off-line data compaction testing with shared resources in PLAs"
Sun, X. and M. Serra
Journal of Semicustom ICs, 8, no. 8, pp. 8-16

"A Lanczos algorithm in a finite field and its application"
Serra, M. and T. Slater
Journal of Combinatorial Mathematics and Combinatorial Computing, 7, pp. 11-32

"The analysis of one-dimensional linear cellular automata and their aliasing properties"
Serra, M., T. Slater, J.C. Muzio and D.M. Miller
IEEE Transactions on CAD, 9, no. 7, pp. 767-778

"The analysis of one dimensional multiple-valued linear cellular automata"
Cattell, K., and M. Serra
Proc. 20th IEEE Int. Symposium on Multiple-Valued Logic,Charlotte, NC. pp. 402-409

"VLSI Design and Test: a Unified Approach"
Serra, M.
Special Issue on Circuits & Systems, IEEE Transactions on Education, 32, no. 3, pp. 237-245

"Space compaction for multiple-output circuits"
Serra, M. and J.C. Muzio
IEEE Transactions on CAD, 7, no. 10, pp. 1105-1114.

"Applications of multi-valued logic to testing of binary and MVL circuits"
Serra, M.
Int. Journal of Electronics, 63, no. 2, pp. 197-214.

"Testing programmable logic arrays by sum of syndromes"
Serra, M. and J.C. Muzio
IEEE Trans. on Computers, C-36, pp. 1097-1101.

"The spectral testing of multiple-output circuits,"
Serra, M. and J.C. Muzio
Developments in Integrated Circuits Testing (D.M. Miller, Editor) Academic Press, 1987, pp.115-145.

"Aliasing probabilities of data compression techniques,"
Muzio, J.C., F.Ruskey, R.C. Aitken and M. Serra
Developments in Integrated Circuits Testing (D.M. Miller, Editor) Academic Press, 1987, pp. 169-218.